Pll circuit

ABSTRACT

An arrangement is provided for reducing phase noise of a phase comparator in a PLL circuit. A voltage controlled oscillator (VCO) responsive to a voltage of an input signal controls a frequency of an output signal. An in-loop frequency divider frequency divides the output signal by two to output two output frequency divided signals. An in-loop phase shifter shifts the output frequency divided signals such that they are different in phase by 360 degrees/2 (e.g., 180 degrees). A reference frequency divider frequency divides a reference signal by two to output two reference frequency divided signals. A reference phase shifter shifts the reference frequency divided signals such that they are different in phase by 180 degrees. A plurality of phase comparators output signals in accordance with phase differences between the output frequency divided signals that are different in phase by 180 degrees and respective reference frequency divided signals that are different in phase by 180 degrees, and an adder sums outputs of the plurality of phase comparators. A low-pass filter passes therethrough and applies the low frequency components of the output of the adder to the voltage controlled oscillator.

TECHNICAL FIELD

The present invention relates to a reduction of a noise in a phasecomparator in a PLL (Phase Locked Loop) circuit.

BACKGROUND ART

Conventionally, there has been used a PLL (Phase Locked Loop) circuit ina frequency multiplier and the like. The PLL circuit includes areference oscillator and a phase comparator. Within a loop bandwidth ofthe PLL circuit, a phase noise of the reference oscillator and a phasenoise of the phase comparator mainly cause a phase noise of the PLLcircuit. An oscillator with a low phase noise such as a crystaloscillator is often used as the reference oscillator. As a result, thephase noise of the PLL circuit is mainly generated by the phase noisedue to the phase comparator.

A technology used to reduce the phase noise of a phase comparator isproposed by Patent Document 1 (U.S. Pat. No. 6,509,800 (Column 7, lines59 to 62, column 11, lines 56 to 60, and FIG. 4)). Namely, there areprovided multiple pairs of a frequency divider which divides an outputfrom a voltage controlled oscillator (VCO) and a phase comparator whichcompares the phase of an output from the frequency divider and the phaseof a reference signal. Noise components of the multiple phasecomparators then are cancelled out mutually by summing the outputs fromthe multiple phase comparators. There can thus be reduced phase noisesof the phase comparators.

However, according to the technology described above, it is necessary toemploy the multiple frequency dividers as many as the number of thephase comparators. As a result, a circuit scale, a cost, and anelectrical power consumption increase accordingly.

An object of the present invention is to provide a simple configurationused to reduce the phase noise of a phase comparator in a PLL circuit.

DISCLOSURE OF THE INVENTION

According to the present invention as described in claim 1, a signalprocessing apparatus includes: a voltage controlled oscillating unitthat controls a frequency of an output signal according to a voltage ofan input signal; an in-loop frequency dividing unit that divides thefrequency of the output signal by M (M is an integer equal to or largerthan two), and outputs M of output frequency divided signals; an in-loopphase shifting unit that shifts the phase of the output frequencydivided signals so that the phases thereof are different from each otherby 360 degrees/M; a reference frequency dividing unit that divides afrequency of a reference signal by M, and outputs M of referencefrequency divided signals; a reference phase shifting unit that shiftsthe phase of the reference frequency divided signals so that the phasesthereof are different from each other by 360 degrees/M; a plurality ofphase comparing units that output signals corresponding to phasedifference among the respective output frequency divided signalsdifferent in phase by 360 degrees/M, and the respective referencefrequency divided signals different in phase by 360 degrees/M; a summingunit that sums the outputs from the phase comparing unit; and a low-passfilter that passes a low frequency component of an output from thesumming unit, and supplies the voltage controlled oscillating unit withthe low frequency component.

According to the present invention configured as described above, avoltage controlled oscillating unit controls a frequency of an outputsignal according to a voltage of an input signal. An in-loop frequencydividing unit divides the frequency of the output signal by M (M is aninteger equal to or larger than two), and outputs M of output frequencydivided signals. An in-loop phase shifting unit shifts the phase of theoutput frequency divided signals so that the phases thereof aredifferent from each other by 360 degrees/M. A reference frequencydividing unit divides a frequency of a reference signal by M, andoutputs M of reference frequency divided signals. A reference phaseshifting unit shifts the phase of the reference frequency dividedsignals so that the phases thereof are different from each other by 360degrees/M. A plurality of phase comparing units output signalscorresponding to phase difference among the respective output frequencydivided signals different in phase by 360 degrees/M, and the respectivereference frequency divided signals different in phase by 360 degrees/M.A summing unit sums the outputs from the phase comparing unit. Alow-pass filter passes a low frequency component of an output from thesumming unit, and supplies the voltage controlled oscillating unit withthe low frequency component.

The present invention as described in claim 2, is the signal processingapparatus according to claim 1, wherein M is obtained by raising two toan integer power.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a block diagram showing a configuration of a PLL circuit 1according an embodiment of the present invention; and

FIG. 2 is a block diagram showing a configuration of a PLL circuit 1according a variation of the embodiment of the present invention.

BEST MODE FOR CARRYING OUT THE INVENTION

A description will now be given of an embodiment of the presentinvention with reference to drawings.

FIG. 1 is a block diagram showing a configuration of a PLL circuit 1according the embodiment of the present invention. The PLL circuit 1 isprovided with a voltage controlled oscillator (VCO) 10, a frequencydivider 12, an in-loop frequency divider 20, an in-loop phase shifterpart 22, a reference signal oscillator 30, a frequency divider 32, areference frequency divider 40, a reference phase shifter part 42, phasecomparators 50 a and 50 b, an adder (summing means) 60, and a loopfilter 70.

The voltage controlled oscillator (VCO) 10 controls a frequency f_(out)of an output signal according to a voltage of an input signal.

The frequency divider 12 divides the frequency of the output signal byN. Note that N is an integer equal to or larger than 2. A fractionalfrequency divider may be added to the frequency divider 12.

The in-loop frequency divider 20 receives the output signal via thefrequency divider 12, divides the frequency thereof by 2, and outputstwo output frequency divided signals.

The in-loop phase shifter part 22 sets the two output frequency dividedsignals such that they are different from each other in phase by 360degrees/2=180 degrees. For example, as shown in FIG. 1, the phase of oneof the two output frequency divided signals is shifted by 180 degrees.

The reference signal oscillator 30 outputs a reference signal with apredetermined frequency of f_(ref).

The frequency divider 32 divides the frequency of the reference signalby R. Note that R is an integer equal to or larger than 2. A fractionalfrequency divider may be added to the frequency divider 32.

The reference frequency divider 40 receives the reference signal via thefrequency divider 32, divides the frequency thereof by 2, and outputstwo reference frequency divided signals.

The reference phase shifter part 42 sets the two reference frequencydivided signals such that they are different from each other in phase by360 degrees/2=180 degrees. For example, as shown in FIG. 1, the phase ofone of the two reference frequency divided signals is shifted by 180degrees.

The phase comparators 50 a and 50 b output signals corresponding torespective phase differences between the output frequency dividedsignals different in phase by 180 degrees and the reference frequencydivided signals different in phase by 180 degrees. Namely, the phasecomparator 50 a outputs a signal corresponding to the phase differencebetween the output frequency divided signal output from the in-loopfrequency divider 20 and the reference frequency divided signal outputfrom the reference frequency divider 40. The phase comparator 50 boutputs a signal corresponding to the phase difference between theoutput frequency divided signal output from the in-loop frequencydivider 20 and then phase shifted by 180 degrees by the in-loop phaseshifter part 22, and the reference frequency divided signal output fromthe reference frequency divider 40 and then phase shifted by 180 degreesby the reference phase shifter part 42.

The adder (summing means) 60 outputs a sum of an output from the phasecomparator 50 a and an output from the phase comparator 50 b.

The loop filter 70 passes low frequency components of the output fromthe adder 60, and supplies the voltage controlled oscillator 10 with thelow frequency components.

A description will now be given of an operation of the embodiment of thepresent invention.

The voltage controlled oscillator 10 outputs the output signal with thefrequency of f_(out). The output signal is frequency divided by thefrequency divider 12 by N, becomes the signal with the frequency off_(out)/N, and is supplied to the in-loop frequency divider 20. Thein-loop frequency divider 20 divides the frequency of the output signalwhich has become f_(out)/N by 2, and outputs the two output frequencydivided signals. The one of the output frequency divided signals isdirectly supplied to the phase comparator 50 a. The other of the outputfrequency divided signals is phase shifted by the in-loop phase shifterpart 22 by 180 degrees, and is supplied to the phase comparator 50 b.

Moreover, the reference signal oscillator 30 outputs the referencesignal with the predetermined frequency of f_(ref). The output signal isfrequency divided by the frequency divider 32 by R, becomes the signalwith the frequency of f_(ref)/R, and is supplied to the referencefrequency divider 40. The reference frequency divider 40 divides thefrequency of the reference signal which has become f_(ref)/R by 2, andoutputs the two reference frequency divided signals. The one of thereference frequency divided signals is directly supplied to the phasecomparator 50 a. The other of the reference frequency divided signals isphase shifted by the reference phase shifter part 42 by 180 degrees, andis supplied to the phase comparator 50 b.

The phase comparators 50 a and 50 b respectively output the signalcorresponding to the phase difference between the input signals. Theseoutputs are summed by the adder 60. The low frequency components of theoutput from the adder 60 pass the loop filter 70, and are supplied tothe voltage controlled oscillator 10.

According to the embodiment of the present invention, a feedback loop isconfigured as described above, and there is thus providedf_(out)=f_(ref)×2N/2R=f_(ref)×N/R. It is possible to set f_(out) to adesired frequency by properly setting N and R.

On this occasion, a term of a phase noise corresponding to f_(ref)within a loop bandwidth is represented as 10 log(f_(ref)/2R) due to thepresence of the reference frequency divider 40. Moreover, a phase noiseincreased twice by the in-loop frequency divider 20 is cancelled byemploying the two phase comparators (phase comparators 50 a and 50 b),resulting in the phase noise being one second. On the other hand, anordinary PLL circuit does not include the reference frequency divider40, the in-loop frequency divider 20, and the phase comparator 50 b, andthe term of the phase noise corresponding to f_(ref) within the loopbandwidth is thus represented as 10 log (f_(ref)/R). As a result, thepresence of the reference frequency divider 40, the in-loop frequencydivider 20, and the phase comparator 50 b increases the phase noise by10 log(f_(ref)/2R)−10 log(f_(ref)/R)=10 log(½)=−3 [dB]. Namely, thephase noise is reduced by 3 [dB].

According to the embodiment of the present invention, there is providedan advantage that although the phase noise is reduced in this way, thereis only necessary the one frequency divider 12. Compared with a casewhere the technology according to Patent Document 1 referenced as priorart is applied to the embodiment of the present invention, and there isthus required two of the frequency dividers 12, which corresponds to thenumber of the phase comparators 50 a and 50 b, there are brought aboutreductions of a circuit scale, a cost, and a power consumption.

Note that a ½ frequency divider is used as the reference frequencydivider 40 according to the embodiment of the present invention.However, it is possible to use a 1/M frequency divider (M is an integerequal to or more than two) as the reference frequency divider 40. Forexample, there may be provided a specification M=2^(n) (n is an integerequal to or more than two). FIG. 2 shows a configuration of the PLLcircuit 1 where M=2²=4.

As FIG. 2 shows, a ¼ frequency divider may be used as the referencefrequency divider 40. In this case, a ¼ frequency divider is used alsoas the in-loop frequency divider 20. The reference frequency divider 40outputs four reference frequency divided signals, and the in-loopfrequency divider 20 also outputs four output frequency divided signals.The four reference frequency divided signals are set such that they aredifferent from each other in phase by 360 degrees/4=90 degrees byreference phase shifter parts 42 a, 42 b, and 42 c. The four outputfrequency divided signals are set such that they are different from eachother in phase by 360 degrees/4=90 degrees by in-loop phase shifterparts 22 a, 22 b, and 22 c. Phase comparators 50 a, 50 b, 50 c, and 50 doutput signals corresponding to respective phase differences among thefour reference frequency divided signals and the four output frequencydivided signals, and the adder 60 sums the outputs.

In the example shown in FIG. 2, the term of the phase noisecorresponding to f_(ref) in the loop bandwidth is represented as 10log(f_(ref)/4R) due to the presence of the reference frequency divider40. Moreover, a phase noise increased four times by the in-loopfrequency divider 20 is cancelled by employing the four phasecomparators (phase comparators 50 a, 50 b, 50 c, and 50 d), resulting inthe phase noise being one fourth. On the other hand, an ordinary PLLcircuit does not include the reference frequency divider 40, the in-loopfrequency divider 20, and the phase comparators 50 b, 50 c, and 50 d,and the term of the phase noise corresponding to f_(ref) within the loopbandwidth is thus represented as 10 log (f_(ref)/R). As a result, thepresence of the reference frequency divider 40, the in-loop frequencydivider 20, and the phase comparators 50 b, 50 c, and 50 d increases thephase noise by 10 log(f_(ref)/4R)−10 log(f_(ref)/R)=10 log(¼)=−6 [dB].Namely, the phase noise is reduced by 6 [dB]. In this way, the phasenoise is reduced by 10 log M [dB].

Moreover, there is provided an advantage that although the phase noiseis reduced in this way, there is only necessary the one frequencydivider 12. Compared with a case where the technology according toPatent Document 1 referenced as prior art is applied to the variation ofthe embodiment of the present invention, and there is thus required fourof the frequency dividers 12, which corresponds to the number of thephase comparators 50 a, 50 b, 50 c, and 50 d, there are brought aboutreductions of the circuit scale, the cost, and the power consumption.

1. A signal processing apparatus, comprising: a voltage controlledoscillating means that controls a frequency of an output signalaccording to a voltage of an input signal; an in-loop frequency dividingmeans that divides the frequency of the output signal by M (where M isan integer at least equal to two), and outputs M of output frequencydivided signals; an in-loop phase shirting means that shifts a phase ofthe output frequency divided signals so that phases thereof aredifferent from each other by 360 degrees/M; a reference frequencydividing means that divides a frequency of a reference signal by M, andoutputs M reference frequency divided signals; a reference phaseshifting means that shifts a phase of the reference frequency dividedsignals so that phases thereof are different from each other by 360degrees/M; a plurality of phase comparing means that output signalscorresponding to a phase difference among respective output frequencydivided signals different in phase by 360 degrees/M, and respectivereference frequency divided signals different in phase by 360 degrees/M;a summing means that sums the outputs from the plurality of phasecomparing means; and a low-pass filter that passes a low frequencycomponent of an output from said summing means, and supplies saidvoltage controlled oscillating means with the low frequency component.2. The signal processing apparatus according to claim 1, wherein M isobtained by raising two to an integer power.
 3. A signal processingapparatus, comprising: a voltage controlled oscillator that controls afrequency of an output signal according to a voltage of an input signal;an in-loop frequency divider that divides the frequency of the outputsignal by M (where M is an integer at least equal to two), and outputs Moutput frequency divided signals; an in-loop phase shifter that shifts aphase of the output frequency divided signals so that phases thereof aredifferent from each other by 360 degrees/M; a reference frequencydivider that divides a frequency of a reference signal by M, and outputsM reference frequency divided signals; a reference phase shifter thatshifts a phase of the reference frequency divided signals so that phasesthereof are different from each other by 360 degrees/M; a plurality ofphase comparators that output signals corresponding to a phasedifference among respective output frequency divided signals differentin phase by 360 degrees/M, and respective reference frequency dividedsignals different in phase by 360 degrees/M; an adder that sums outputsfrom the plurality of phase comparators; and a low-pass filter thatpasses a low frequency component of an output from said summer, andsupplies said voltage controlled oscillator with the low frequencycomponent.
 4. The signal processing apparatus of claim 1, wherein M isobtained by raising two to an integer power.